To convert a supply voltage Vin to an output voltage Vout, as shown in FIG. 1, a typical linear voltage regulator 10 comprises a transistor 16 coupled between the power input node Vin and the power output node Vout, and being controlled to regulate the output voltage Vout. In addition, a bypass capacitor C is coupled between the output Vref of a reference voltage generator 12 and ground GND to stabilize the reference voltage Vref, voltage divider resistors R1 and R2 coupled between the power output node Vout and ground GND divides the output voltage Vout to produce a feedback signal VFB, and an error amplifier 14 compares the feedback signal VFB with the reference voltage Vref to determine an error signal VEA which is coupled to the gate of the transistor 16 to adjust the channel width of the transistor 16. In this circuit configuration, the Power Supply Reject Ratio (PSRR) of the output voltage Vout is contributed from the PSRR of the reference voltage Vref and the PSRR of the error signal VEA. Particularly, in high frequency applications, ranged from several tens of KHz to hundreds of KHz, such as wireless communications, the output voltage Vout is required to be highly stable. Ideally, both the reference voltage Vref and the supply voltage Vin are constant, however, it is not the case actually. Ripple may occur on the reference voltage Vref, and thereby results in perturbation on the output voltage Vout. For this reason, it is a simple and common resolution to use the bypass capacitor C to reduce the ripple on the reference voltage Vref, to thereby improve the PSRR of the output voltage Vout. Not only the reference voltage Vref, the supply voltage Vin may also have a ripple, which would also cause a perturbation on the output voltage Vout. When the supply voltage Vin suffers a ripple, it causes the output voltage Vout varying, and this information will be reflected on the feedback voltage VFB. Through the error amplifier 14 feedback loop, the channel width of the transistor 16 will be adjusted to stable the output voltage Vout. When the bypass capacitor C is maximized, the total loop PSRR is still limited by the error amplifier 14 and transistor 16 feedback loop response. In addition, sensing the output response to improve the PSRR always lags since the output voltage Vout has already dropped or raised. Therefore, the linear voltage regulator 10 cannot respond rapidly to the input transient when the supply voltage Vin suffers a ripple. To solve this problem, conventionally, circuit designers focus on improving the response time of the error amplifier 14 or the feedback loop. However, no matter how fast the response time of the error amplifier 14 or the feedback loop is improved, it is still established through the feedback loop based on the output voltage Vout, and the linear voltage regulator 10 always responds after the output voltage Vout suffers the perturbation resulted from the ripple on the supply voltage Vin. More severely, altering the response time of the error amplifier 14 or the feedback loop may also change the original stability range and compensation of the linear voltage regulator 10.
Therefore, it is desired a linear voltage regulator which can eliminate the influence of the supply voltage ripple before it causes a perturbation on the output voltage.